1. Field of the Invention
The present invention relates, generally, to communication systems and processes which use phase lock loops, and, in particular embodiments, to systems and processes which use phase lock loops as translation loops in the process of modulation.
2. Description of Related Art
It has become increasingly important to minimize the cost of various electronic devices, especially personal communication devices such as cellular telephones, cordless telephones, and the like. One way to minimize the cost of such devices is to minimize the number of components and functions required in the electronic device. Another way to miniimize cost is to use the same component to perform different functions in different applications. Personal communication devices, however, often require complex circuitry with a number of components for performing particular functions. This is especially true in modern cellular phone communications.
One of the circuits that has been particularly useful in communications electronics is the Phase Lock Loop (PLL). A phase lock loop (PLL) circuit is a circuit that is used for the synchronization of signals. Phase lock loops are used in a wide variety of electronic circuits, in which signals, containing analog and digital information, are decoded. Phase lock loops may be thought of as synchronizing circuits, in which an output frequency is synchronized, or locked, to a reference frequency. PLLs are also used in mobile communication applications related to such purposes as frequency generation, signal modulation, signal demodulation, data decoding and data encoding.
PLLs are unsynchronized when they have no reference signal. In the unsynchronized condition PLLs are said to be unlocked, or out of lock. Phase lock loops generally work by comparing a reference frequency to a generated output frequency and adjusting the output frequency to match the reference frequency. As the output signal is adjusted by the loop, there occurs a point, at which the frequencies of the output and reference signals match. At the point, that frequencies of the output and reference signals match, the signals are sometimes said to be in frequency lock. When the generated frequency is further synchronized in phase with the input frequency, the frequencies are commonly said to be in phase lock, the locked state, or simply lock. During lock, when the output frequency is synchronized with the reference frequency, the phase error, between the output frequency and reference frequency, may be very small or even zero. The output signal will generally stay in the lock state until the phase lock loop is somehow perturbed.
Phase lock loops have application not only in frequency synchronization, but also in frequency synthesis, and frequency generation. PLL's may incorporate divider, multiplier, or mixer circuits in order to create lower, higher, or translated frequencies.
Even though the practice of translating frequencies can be accomplished by phase lock loops, translating frequencies can also be accomplished by mixer circuits. Mixer circuits can inject noise into the system which must be then attenuated using filters or other means. Noise within these circuits can be problematical and degrade circuit performance. Current mixer circuits and PLL translation circuits, are not helpful in attenuating circuit noise and may even inject further noise to these circuits.